The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low RC (resistance capacitance) metal interconnect properties, particularly wherein submicron via/contact holes (inter-layer interconnects) and intra-layer interconnects with increasingly high aspect ratios.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision of a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects (wiring) and inter-layer conductive interconnects formed by openings or holes in an insulating layer (inter-metal dielectric layer). Such holes are commonly referred to as vias, for example, when the hole extends through an insulating layer between two conductive layers. The intra-layer interconnects, for example, trench lines are formed in dielectric insulating layers and backfilled with metal and frequently referred to as metallization layers. In one manufacturing approach, trench lines are formed overlying and encompassing vias to form dual damascene interconnect structures.
In a typical process for forming multiple layer interconnect structure, for example, a dual damascene process, an insulating inter-metal dielectric (IMD) layer is deposited over a conductive area, for example a metallization layer frequently referred to as M1, M2, M3, etc. depending on the number of preceding metallization layers. In one approach to forming a dual damascene structure a high aspect ratio opening referred to as a via is then anisotropically etched through the IMD layer by conventional photolithographic and etching techniques. Another anisotropically etched opening referred to as a trench line is then formed according to a second photolithographic patterning process overlying and encompassing the via opening. The via opening and the trench line together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a (chemical mechanical polishing (CMP) process to planarize the wafer process surface and prepare the process surface for formation of another layer or level in a multi-layered semiconductor device.
Signal transport speed is of great concern in the semiconductor processing art for obvious performance reasons. The signal transport speed of semiconductor circuitry, also referred to as the RC time constant, varies inversely with the resistance and capacitance (RC) of the interconnections. As integrated circuits become more complex and feature sizes decrease, the effect of the RC time constant on signal delay becomes greater.
Copper (Cu) and copper alloys are increasingly being used for the conductive metal filling in damascene and dual damascene structures. Copper has a lower resistivity and consequently produces less current heating and signal delay associated with the RC time constant in increasingly faster circuits. The use of copper for device interconnects has created a number of new technological problems in semiconductor device manufacturing that must be overcome to provide reliable devices. One problem with copper interconnects has been the fact that copper readily diffuses through silicon dioxide or silicon dioxide based materials, a typical IMD material. The diffusion of copper into the IMD layer reduces both the effectiveness of the electrical interconnect and the electrical insulation properties of the IMD layers. Another problem is that copper has poor adhesion to silicon dioxide based IMD layers. The technological difficulties associated with the use of copper have additionally manifested themselves in parallel efforts to reduce the capacitance contribution of the IMD layers to the RC time constant, such reduction being necessary to achieve increased signal transport speeds. For example, by lowering both the dielectric constant of the insulating material used to form the IMD layer and reducing the thickness, the capacitance contribution of the IMD layer is reduced thereby allowing faster signal transport. One difficulty is that the reduced strength of low-k materials in combination with thinner layers frequently results in cracking when such materials are subjected to thermal stresses.
Typical low-k (low dielectric constant) materials in use have included carbon doped silicon dioxide such as commercially available BLACK DIAMOND™ and other materials tend to form a porous material thereby reducing the overall dielectric constant. Porous low-k materials have a drawback in that the porosity tends to weaken the overall strength and hardness of the material making crack initiation and propagation more likely. As the requirement for device density increases, the number of levels in a device has increased to 4 to 7 levels. The increased number of material layers contributes the buildup of compressive and tensile stresses in the multiple layers, especially when subjected to thermal stresses, which frequently do not offset one another. The result is that cracking becomes more likely as the number of device layers increase and the process wafer is subjected to externally induced cycling stresses including thermal heating and cooling.
For example, in the use of copper or copper alloys for forming conductive interconnects, it has been found to that electroplating of copper has many advantages over other methods such as PVD or CVD methods of deposition, such as superior step coverage for high aspect ratio openings. Following electrodeposition, a CMP process is carried out to remove excess deposited copper and to planarize the process surface for subsequent layer formation. Frequently, the copper filling is subjected to a thermal annealing treatment approaching 400° C. to improve the metallurgical qualities of the copper. In addition, the deposition of an overlying etching stop layer such as silicon nitride, silicon oxynitride or silicon carbide by plasma enhanced CVD techniques typically requires a wafer substrate heated to about 400° C. Other processing steps including plasma pre-cleaning processes prior to a material layer deposition may also include temperatures subjecting the wafer to thermal stresses.
One particular serious problem that requires a solution is the tendency for copper filled damascene structures that are in upper levels, for example, above about metallization layer 3 to exhibit crack initiation and propagation through low-k IMD layers as a result of thermal cycling stresses. The problem of cracking is exacerbated in a multiple layer structure where multiple stresses in the various layers may combine to achieve stresses necessary for crack initiation and propagation. The propagation of cracks through the IMD layer is catastrophic to device functioning and frequently requires the scraping of a process wafer.
It is therefore an object of the invention to develop a method for semiconductor manufacturing of damascene structures that will prevent crack initiation and propagation in low-k IMD layers while overcoming other shortcomings and deficiencies in the prior art.